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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2008 pc755/745 powerpc 755/745 risc microprocessor datasheet 0828i?hirel?01/08 features 18.1specint95, estimates 12.3 specfp95 at 400 mhz (pc755) 15.7specint95, 9specfp95 at 350 mhz (pc745) 733 mips at 400 mhz (pc755) at 641 mips at 350 mhz (pc745) selectable bus clock (12 cp u bus dividers up to 10x) p d typical 6.4w at 400 mhz, full operating conditions nap, doze and sleep modes for power savings superscalar (3 instructions per cl ock cycle) two instruction + branch 4 beta byte virtual memory, 4-gbyte of physical memory 64-bit data and 32-bit address bus interface 32-kb instruction and data cache six independent execution units write-back and write-through operations f int max = 400 mhz (tbc) f bus max = 100 mhz voltage i/o 2.5v/3.3v; voltage int 2.0v description the pc755 and pc745 powerpc ? microprocessors are high-performance, low-power, 32-bit implementations of the pow- erpc reduced instruction set computer (risc) archit ecture, especially enhanced for embedded applications. the pc755 and pc745 microprocessors differ only in that the pc755 features an enhanced, dedicated l2 cache interface with on-chip l2 tags. the pc755 is a drop-in replacement for the award winning powerpc 750 microprocessor and is foot- print and user software code compatible with the mpc7400 microprocessor with altivec ? technology. the pc745 is a drop- in replacement for the powerpc 740 microprocessor and is also footprint and user software code compatible with the pow- erpc 603e microprocessor. pc755/745 microprocessors provide on-chip debug support and are fully jtag-compliant. the pc745 microprocessor is pin compatible with the tspc603e family. screening this product is manufactured in full compliance with: hitce cbga according to e2v standards cbga + ci-cga + fc-pbga up scree nings based upon e2v standards full military temperature ranges (t c = -55c, t j = +125c) industrial temperature ranges (t c = -40 c, t j = +110 c)
2 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 1. general description 1.1 simplified block diagram the pc755 is targeted for low power systems and supports power management features such as doze, nap, sleep, and dynamic power management. the pc755 consists of a processor core and an internal l2 tag combined with a dedicated l2 cache interface and a 60x bus. figure 1-1. pc755 block diagram additional features * time base counter/decrementer * clock multiplier * jtag/cop interface * thermal/power management * performance monitor + + fetcher branch processing btic 64-entry + x : fpscr cr fpscr l2cr ctr lr bht data mmu instruction mmu not in the pc745 ea pa + x : instruction unit unit instruction queue (6-word) 2 instructions reservation station reservation station reservation station integer unit 1 system register unit dispatch unit 64-bit (2 instructions) srs itlb (shadow) ibat array 32-kbyte i cache tags 128-bit (4 instructions) reservation station 32-bit floating-point unit rename buffers (6) fpr file 32-bit 64-bit 64-bit reservation station (2-entry) load/store unit (ea calculation) store queue gpr file rename buffers (6) 32-bit srs (original) dtlb dbat array 64-bit completion unit reorder buffer (6-entry) tags 32-kbyte d cache 60x bus interface unit instruction fetch queue l1 castout queue data load queue l2 controller l2 tags l2 bus interface unit l2 castout queue 32-bit address bus 32-/64-bit data bus 17-bit l2 address bus 64-bit l2 data bus integer unit 2
3 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 1.2 general parameters the following list provides a summary of the general parameters of the pc755: 1.3 features this section summarizes features of the pc755?s implementation of the powerpc architecture. major features of the pc755 are as follows: branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving 2 speculations) ? up to 1 speculative stream in execution, 1 additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots dispatch unit ? full hardware detection of dependencies (resolved in the execution units) ? dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point) ? serialization control (predispatch, pos tdispatch, execution serialization) decode ? register file access ? forwarding control ? partial instruction decode completion ? 6 entry completion buffer ? instruction tracking and peak comple tion of two instructions per cycle ? completion of instructions in program order while supporting out-of-order instruction execution, completion serializatio n and all instruction flow changes technology 0.22 m cmos, five-layer metal, 1 layer poly die size 6.61 mm x 7.73 mm (51 mm 2 ) transistor count 6.75 million logic design fully-static packages pc745 surface mount 255 plastic ball grid array (pbga) surface mount 255 ceramic ball grid array (hi-tce) pc755 surface mount 360 plastic ball grid array (pbga) surface mount 360 ceramic ball gr id array (ci-cga, cbga, hitce) core power supply 2v 100 mv dc (nominal; some parts support core voltages down to 1.8v; see ?recommended operating conditions (1) ? on page 16 i/o power supply 2.5v 100 mv dc or 3.3v 165 mv dc (input thresholds are configuration pin selectable)
4 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 fixed point units (fxus) that share 32 gprs for integer operands ? fixed point unit 1 (fxu1)-multiply, di vide, shift, rotate, arithmetic, logical ? fixed point unit 2 (fxu2)-shi ft, rotate, arithmetic, logical ? single-cycle arithmetic, shifts, rotates, logical ? multiply and divide support (multi-cycle) ? early out multiply floating-point unit and a 32-entry fpr file ? support for ieee ? -754 standard single and double precision floating point arithmetic ? hardware support for divide ? hardware support for denormalized numbers ? single-entry reservation station ? supports non-ieee mode for time-critical operations system unit ? executes cr logical instructions and miscellaneous system instructions ? special register transfer instructions load/store unit ? one cycle load or store cache access (byte, half-word, word, double-word) ? effective address generation ? hits under misses (one outstanding miss) ? single-cycle unaligned access within double word boundary ? alignment, zero padding, sign extend for integer register file ? floating point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering ? cache and tlb instructions ? big and little-endian byte addressing supported ? misaligned little-endian supported ? level 1 cache structure ? 32k, 32 bytes line, 8-way set associative instruction cache (il1) ? 32k, 32 bytes line, 8-way set associative data cache (dl1) ? cache locking for both instruction and data caches, selectable by group of ways ? single-cycle cache access ? pseudo least-recently used (plru) replacement ? copy-back or write through data cache (on a page per page basis) ? supports all powerpc memory coherency modes ? non-blocking instruction and data cache (one outstanding miss under hits) ? no snooping of instruction cache level 2 (l2) cache interface (not implemented on pc745) ? internal l2 cache controller and tags; external data srams ? 256k, 512k, and 1-mbyte 2-way set associative l2 cache support
5 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 ? copyback or write-through data cache (on a page basis, or for all l2) ? instruction-only mode and data-only mode. ? 64 bytes (256k/512k) or 128 bytes (1m) sectored line size ? supports flow through (register-buffer) synchronous burst srams, pipelined (register- register) synchronous burst srams (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register- register) late-write synchronous burst srams ? l2 configurable to direct mapped sram interface or split cache/direct mapped or private memory ? core-to-l2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported ? 64-bit data bus ? selectable interface voltages of 2.5v and 3.3v ? parity checking on both l2 address and data memory management unit ? 128 entry, 2-way set associative instruction tlb ? 128 entry, 2-way set associative data tlb ? hardware reload for tlbs ? hardware or optional software tablewalk support ? 8 instruction bats and 8 data bats ? 8 sprgs, for assistance with software tablewalks ? virtual memory support for up to 4 hexabytes (2 52 ) of virtual memory ? real memory support for up to 4 gigabytes (2 32 ) of physical memory bus interface ? compatible with 60x processor interface ? 32-bit address bus ? 64-bit data bus, 32-bit mode selectable ? bus-to-core frequency multipliers of 2x, 3x, 3.5x , 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x supported ? selectable interface voltages of 2.5v and 3.3v. ? parity checking on both address and data busses power management ? low-power design with thermal requirements very similar to pc740/750. ? selectable interface voltage of 1.8v/2.0v can reduce power in output buffers (compared to 3.3v) ? three static power saving modes: doze, nap, and sleep ? dynamic power management testability ? lssd scan design ? ieee 1149.1 jtag interface integrated thermal management assist unit ? one-ship thermal sensor and control logic ? thermal management interrupt for software regulation of junction temperature
6 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 2. pin assignments figure 2-1 (in part a) shows the pinout of the pc745, 255pbga and hitce cbga packages as viewed from the top surface. part b shows the side profile of the pbga package to indicate the direction of the top surface view. figure 2-1. pinout of the pc745, 255 pbga and hitce cbga pa ckages as viewed from the top surface figure 2-2 (in part a) shows the pinout of the pc755, 360 pbga packages as viewed from the top sur- face. part b shows the side profile of the pbga package to indicate the direction of the top surface view. a b c d e f g h j k l m n p r t not to scale view die substrate assembly encapsulant part b part a 12345678 9 10 11 12 13 14 15 16
7 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 figure 2-2. pinout of the pc755, 360 pbga, cbga, hitce cbga and ci-cga packages as viewed from the top surface a b c d e f g h j k l m n p r t not to scale u v w view die substrate assembly encapsulant part b part a 1 2345678 9 10 11 12 13 14 15 16 17 18 1 9
8 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 2.1 pinout listings table 2-1 provides the pinout listing for the pc745, 255 pbga package. table 2-1. pinout listing for the pc745, 255 pbga and hitce cbga packages signal name pin number active i/o i/f voltages supported (1) 1.8v/2.0v 3.3v a[0 - 31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o ? ? aack l2 low input ? ? abb k4 low i/o ? ? ap[0 - 3] c1, b4, b3, b2 high i/o ? ? artry j4 low i/o ? ? avdd a10 ? ? 2v 2v bg l1 low input ? ? br b6 low output ? ? bvsel (3)(4)(5) b1 high input gnd 3.3v ci e1 low output ? ? ckstp_in d8 low input ? ? ckstp_out a6 low output ? ? clk_out d7 ? output ? ? dbb j14 low i/o ? ? dbg n1 low input ? ? dbdis h15 low input ? ? dbwo g4 low input ? ? dh[0 - 31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o ? ? dl[0 - 31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n 10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 high i/o ? ? dp[0 - 7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o ? ? drtry g16 low input ? ? gbl f1 low i/o ? ? gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 hreset a7 low input ? ? int b15 low input ? ? l1_tstclk (2) d11 high input ? ? l2_tstclk (2) d12 high input ? ?
9 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals and v dd supplies power to the processor core and the pll (after filtering to become avdd). these columns serve as a reference for the nominal voltage supported on a given signal as selected by the bvsel pin configuration of table 5-1 on page 15 and the voltage supplied. for actual recom- mended value of v in or supply voltages see ?absolute maximum ratings (1) ? on page 14 . 2. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 3. to allow for future i/o voltage changes, provide the option to connect bvsel independently to either ov dd (selects 3.3v) or to ognd (selects 1.8v/2.0v). 4. uses one of 15 existing no - connects in pc745?s 255 - bga package. lssd_mode (2) b10 low input ? -? mcp c13 low input ? ? nc (no - connect) b7, b8, c3, c6, c8, d5, d6 , h4, j16, a4, a5, a2, a3, b5 ? ? ? ? ovdd c7, e5, e7, e10, e12, g3, g5, g12, g14, k3, k5, k12, k14, m5, m7, m10, m12, p7, p10 ? ? 1.8v/2.0v 3.3v pll_cfg[0 - 3] a8, b9, a9, d9 high input ? ? qack d3 low input ? ? qreq j3 low output ? ? rsrv d1 low output ? ? smi a16 low input ? ? sreset b14 low input ? ? sysclk c9 ? input ? ? ta h14 low input ? ? tben c2 high input ? ? tbst a14 low i/o ? ? tck c11 high input ? ? tdi (5) a11 high input ? ? tdo a12 high output ? ? tea h13 low input ? ? tlbisync c4 low input ? ? tms (5) b11 high input ? ? trst (5) c10 low input ? ? ts j13 low i/o ? ? tsiz[0 - 2] a13, d10, b12 high output ? ? tt[0 - 4] b13, a15, b16, c14, c15 high i/o ? ? wt d2 low output ? ? v dd 2 f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9, l11 ? ? 2v 2v voltdet (6) f3 high output ? ? table 2-1. pinout listing for the pc745, 255 pbga and hitce cbga packages (continued) signal name pin number active i/o i/f voltages supported (1) 1.8v/2.0v 3.3v
10 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 5. internal pull up on die. 6. internally tied to gnd in the pc745 255 - bga package to indicate to the power supply that a low - voltage processor is present. this signal is not a power supply input. table 2-2 provides the pinout listing for the pc755, 360 pbga, cbga, hitce cbga and ci-cga table 2-2. pinout listing for the pc755, 360 pbga, cbga, hitce cbga and ci-cga packages (8) signal name pin number active i/o i/f voltages supported (1) 1.8v/2.0v 3.3v a[0 - 31] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7, e1, g2 , f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o ? ? aack n3 low input ? ? abb l7 low i/o ? ? ap[0 - 3] c4, c5, c6, c7 high i/o ? ? artry l6 low i/o ? ? avdd a8 - - 2v 2v bg h1 low input ? ? br e7 low output ? ? bvsel (3)(5)(6) w1 high input gnd 3.3v ci c2 low output ? ? ckstp_in b8 low input ? ? ckstp_out d7 low output ? ? clk_out e3 ? output ? ? dbb k5 low i/o ? ? dbdis g1 low input ? ? dbg k1 low input ? ? dbwo d1 low input ? ? dh[0 - 31] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o ? ? dl[0 - 31] m6, p3, n4, n5, r3, m7, t2, n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o ? ? dp[0 - 7] l1, p2, m2, v2, m1, n2, t3, r1 high i/o ? ? drtry h6 low input ? ? gbl b1 low i/o ? ? gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r12, t4, t6, t10, t14, t16 ??gndgnd hreset b6 low input ? ?
11 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 int c11 low input ? ? l1_tstclk (2) f8 high input ? ? l2addr[0 - 16] l17, l18, l19, m19, k18, k17, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output ? ? l2avdd l13 ? ? 2v 2v l2ce p17 low output ? ? l2clkouta n15 ? output ? ? l2clkoutb l16 ? output ? ? l2data[0 - 63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a15, c15, b14, c14, e13 high i/o ? ? l2dp[0 - 7] v14, u16, t19, n18, h14, f17, c19, b15 high i/o ? ? l2ovdd d15, e14, e16, h16, j15, l15, m16, p15, r14, r16, t 15, f15 ? ? 1.8v/2v 3.3v l2sync_in l14 ? input ? ? l2sync_out m14 ? output ? ? l2_tstclk (2) f7 high input ? ? l2vsel (1)(3)(5)(6) a19 high input gnd 3.3v l2we n16 low output ? ? l2zz g17 high output ? ? lssd_mode (2) f9 low input ? ? mcp b11 low input ? ? nc (no - connect) b3, b4, b5 , w19, k9, k11 4 , k19 4 ?? ? ? ovdd d5, d8, d12, e4, e6, e9 , e11, f5, h4, j5, l5 , m4, p5, r4, r6, r9, r11, t5, t8, t12 ? ? 1.8v/2v 3.3v pll_cfg[0 - 3] a4, a5, a6, a7 high input ? ? qack b2 low input ? ? qreq j3 low output ? ? rsrv d3 low output ? ? smi a12 low input ? ? sreset e10 low input ? ? sysclk h9 ? input ? ? ta f1 low input ? ? tben a2 high input ? ? table 2-2. pinout listing for the pc755, 360 pbga, cbga, hitce cbga and ci-cga packages (8) (continued) signal name pin number active i/o i/f voltages supported (1) 1.8v/2.0v 3.3v
12 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 notes: 1. ov dd supplies power to the processor bus, jtag, and all contro l signals except the l2 cache controls (l2ce, l2we, and l2zz); l2ov dd supplies power to the l2 cache interface (l2addr[0 - 16], l2data[0 - 63], l2dp[0 - 7] and l2sync - out) and the l2 control signals; and v dd supplies power to the processor core and the pll and dll (after filtering to become av dd and l2av dd respectively). these columns serve as a reference fo r the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin configurations of table 5-1 on page 15 and the voltage supplied. for actual recom- mended value of v in or supply voltages see ?recommended operating conditions (1) ? on page 16 . 2. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 3. to allow for future i/o voltage changes, provide the option to connect bvsel and l2vsel independently to either ov dd (selects 3.3v) or to ognd (selects 1.8v/2.0v). 4. these pins are reserved for potential future use as additional l2 address pins. 5. uses one of 9 existing no - connects in pc750?s 360 - bga package. 6. internal pull up on die. 7. internally tied to l2ov dd in the pc755 360 - bga package to indicate the power present at the l2 cache interface. this signal is not a power supply input. 8. this is different from the pc745 255-bga package. tbst a11 low i/o ? ? tck b10 high input ? ? tdi (6) b7 high input ? ? tdo d9 high output ? ? tea j1 low input ? ? tlbisync a3 low input ? ? tms (6) c8 high input ? ? trst (6) a10 low input ? ? ts k7 low i/o ? ? tsiz[0 - 2] a9, b9, c9 high output ? ? tt[0 - 4] c10, d11, b12, c12, f11 high i/o ? ? wt c3 low output ? ? vdd g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 ? ? 2v 2v voltdet (7) k13 high output ? ? table 2-2. pinout listing for the pc755, 360 pbga, cbga, hitce cbga and ci-cga packages (8) (continued) signal name pin number active i/o i/f voltages supported (1) 1.8v/2.0v 3.3v
13 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 3. signal description figure 3-1. pc755 microprocessor signal groups br bg abb ts tt[0-4] ap[0-3] tbst ts1z[0-2] gbl wt ci aack artry dbg dbwo dbb l2addr [16-0] l2data [0-63] l2dp [0-7] l2clk-out [a-b] l2we a[0-31] l2sync_out l2sync_in int smi mcp hreset ckstp_in ckstp_out sysclk, pll_cfg [0-3] 4 17 64 8 factory test jtag:cop address arbitration address start address bus transfer attribute address termination data arbitration l2 cache l2 vsel address/ data l2 cache clock/control interrupts reset clock control test interface 1 1 2 1 1 1 1 1 1 5 3 1 1 1 1 1 32 4 5 3 1 1 1 1 1 1 d[0-63] data transfer d[p0-7] dbdis ta data termination drtry tea pc755b l2av dd l2v dd sreset 1 1 rsrv tben tlbisync qreq qack processor status control clk_out 1 1 1 1 1 1 1 1 v dd av dd l2ce l2zz not supported in the pc745b 1 1 8 1 1 1 11 64 gnd ov dd voltdet
14 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 4. detailed specifications this specification describes the sp ecific requirements for the microprocessor pc755, in compliance with e2v grenoble standard screening. 5. applicable documents 1) mil-std-883: test methods and procedures for electronics. 2) mil-prf-38535 appendix a: general specifications for microcircuits. the microcircuits are in accordance with the applicable documents and as specified herein. 5.1 design and construction 5.1.1 terminal connections depending on the package, the terminal connections is shown in table 2-1 on page 8 , table 2-2 on page 10 and figure 3-1 on page 13 . notes: 1. functional and tested operating conditions are given in ?recommended operating conditions (1) ? on page 16 . absolute max- imum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v in must not exceed ov dd or l2ov dd by more than 0.3v at any time including during power-on reset. 3. caution: l2ov dd /ov dd must not exceed v dd /av dd /l2av dd by more than 1.6v during normal operation. during power-on reset and power-down sequences, l2ov dd /ov dd may exceed v dd /av dd /l2av dd by up to 3.3v for up to 20 ms, or by 2.5v for up to 40 ms. excursions beyond 3.3v or 40 ms are not supported. 4. caution: v dd /av dd /l2av dd must not exceed l2ov dd /ov dd by more than 0.4v during normal operation. during power-on reset and power-down sequences, v dd /av dd /l2av dd may exceed l2ov dd /ov dd by up to 1.0v for up to 20 ms, or by 0.7v for up to 40 ms. excursions beyond 1.0v or 40 ms are not supported. 5. this is a dc specifications only. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 5-1 on page 15 . 5.1.2 absolute maximum ratings (1) characteristic symbol maximum value unit core supply voltage (4) v dd -0.3 to 2.5 v pll supply voltage (4) av dd -0.3 to 2.5 v l2 dll supply voltage (4) l2av dd -0.3 to 2.5 v processor bus supply voltage (3) ov dd -0.3 to 3.6 v l2 bus supply voltage (3) l2ov dd -0.3 to 3.6 v input voltage processor bus (2)(5) v in -0.3 to ov dd + 0.3v v l2 bus (2)(5) v in -0.3 to l2ov dd + 0.3v v jtag signals v in -0.3 to 3.6 v storage temperature range t stg -65/+150 c
15 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 figure 5-1 shows the allowable undershoot and overshoot voltage on the pc755 and pc745. figure 5-1. overshoot/undershoot voltage the pc755 provides several i/o volt ages to support both compatibility with exis ting systems and migra- tion to future systems. the pc755 core voltage must always be provided at nominal 2.0v (see ?recommended operating conditions (1) ? on page 16 for actual recommended core voltage). voltage to the l2 i/os and processor interface i/os are provided through separate sets of supply pins and may be provided at the voltages shown in table 5-1 . the input voltage threshold for each bus is selected by sampling the state of the voltage select pins bvsel and l2vsel during operati on. these signals must remain stable during part operation and cannot change. the output voltage will swing from gnd to the maximum voltage applied to the ov dd or l2ov dd power pins. table 5-1 describes the input threshold voltage setting. notes: 1. caution: the input threshold selection must agree with the ov dd /l2ov dd voltages supplied. 2. the input threshold settings above are different for all revision s prior to rev. 2.8 (rev. e). for more information, contact your local e2v sales office. (l2) ov dd +20% (l2) ov dd +5% (l2) ov dd gnd - 1.0v gnd - 0.3v gnd v ih not to exceed 10% of t sysclk v il table 5-1. input threshold voltage setting part revision bvsel signal processor bus interface voltage l2vsel signal l2 bus interface voltag e e 0 not available 0 not available 1 2.5v/3.3v 1 2.5v/3.3v
16 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. revisions prior to rev. 2.8 (rev. e) offered different i/o voltage support. 3. 2.0v nominal. 4. 2.5v nominal. 5. 3.3v nominal. 5.1.3 recommended operating conditions (1) characteristic recommended value unit 300 mhz, 350 mhz 400 mhz symbol min max min max core supply voltage (3) v dd 1.80 2.10 1.90 2.10 v pll supply voltage (3) av dd 1.80 2.10 1.90 2.10 v l2 dll supply voltage (3) l2av dd 1.80 2.10 1.90 2.10 v processor bus supply voltage (2)(4)(5) bvsel = 1 ov dd 2.375 2.625 2.375 2.625 v 3.135 3.465 3.135 3.465 v l2 bus supply voltage (2)(4)(5) l2vsel = 1 l2ov dd 2.375 2.625 2.375 2.625 v 3.135 3.465 3.135 3.465 v input voltage processor bus v in gnd ov dd gnd ov dd v l2 bus v in gnd l2ov dd gnd l2ov dd v jtag signals v in gnd ov dd gnd ov dd v die-junction temperature military temperature range t c = -55 t j = 125 t c = -55 t j = 125 c industrial temperature t c = -40 t j = 110 t c = -40 t j = 110 c
17 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 6. thermal characteristics 6.1 package characteristics table 6-1 provides the package thermal characteristics for the pc755. notes: 1. junction temperature is a function of on-chip power diss ipation, package thermal resistance, mounting site (board) temp era- ture, ambient temperature, air flow, power dissipation of ot her components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 wit h the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circui t board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between th e die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1 c/w. note: refer to section 6.1.3 ?thermal management information? on page 19 for more details about thermal management. 6.1.1 package thermal characteristics for hitce table 6-2 provides the package thermal characteristics for the pc755, hitce. notes: 1. simulation, no convection air flow. 2. per jedec jesd51-6 with the board horizontal. 3. per jedec jesd51-8 4. per jedec jesd51-2 with the board horizontal. table 6-1. package thermal characteristics characteristic symbol value unit pc755 cbga pc755 pbga pc745 pbga junction-to-ambient thermal resistance, natural convection ()(2) r ja 24 31 34 c/w junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board ()(3) r jma 17 25 26 c/w junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board ()(3) r jma 18 25 27 c/w junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board ()(3) r jma 14 21 22 c/w junction-to-board thermal resistance (4) r jb 81717 c/w junction-to-case thermal resistance (5) r jc < 0.1 < 0.1 < 0.1 c/w table 6-2. package thermal characte ristics for hitce package characteristic symbol value unit pc755 hitce pc745 hitce junction-to-bottom of balls (1) r j 6.8 6.5 c/w junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r jma 20.7 (1) (2) 20.9 (1) (4) c/w junction to board thermal resistance r jb 11.0 10.2 (3) c/w
18 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 the board designer can choose between several types of heat sinks to place on the pc755. there are several commercially-available heat sinks for the pc755 provided by the following vendors. for the exposed-die packaging technology, shown in ?recommended operating conditions (1) ? on page 16 , the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (or top-of-die fo r exposed silicon) thermal resistance the die junction-to-ball thermal resistance figure 6-1 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. heat generated on the active side of the chip is conducted through th e silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced- air convection. since the silicon thermal re sistance is quite small, fo r a first-order anal ysis, the temperature drop in the silicon may be neglected. thus, the heat sink atta ch material and the heat sink conducti on/convective thermal resistances are the dominant terms. figure 6-1. c4 package with head sink mounted to a printed-circuit board note the internal versus external package resistance. table 6-3. package thermal characteristics for ci-cga characteristic symbol value unit pc755 ci-cga junction to board thermal resistance r jb 8.42 c/w external resistance external resistance internal resistance radiation convection radiation convection heat sink printed circuit board thermal interface material package/leads die junction die/package
19 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 6.1.2 thermal management assistance the pc755 incorporates a thermal management assist unit (tau) composed of a thermal sensor, digital- to-analog converter, comparator, control logic, and dedicated special-purpose registers (sprs). specifi- cations for the thermal sensor portion of the tau are found in table 6-4 . more information on the use of this feature is given in the freescale ? pc755 risc microprocessor user?s manual. notes: 1. the temperature is the juncti on temperature of the die. the ther mal assist unit?s raw output does not indicate an absolute temperature, but must be interp reted by software to derive the absolute junction temperature. for information about the use and calibra tion of the tau, see freescale application note an1800/d, ?programming the thermal assi st unit in the pc750 microprocessor?. 2. the comparator settling time value must be conver ted into the number of cp u clocks that need to be written into the thrm3 spr. 3. guaranteed by design and characterization. 6.1.3 thermal management information this section provides thermal management informat ion for air-cooled applications. proper thermal con- trol design is primarily dependent upon the system-l evel design-the heat sink, airflow and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see figure 6-2 . this spring force should not exceed 5.5 pounds of force. figure 6-2. package exploded cross-sectional view with several heat sink options ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal per- formance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. table 6-4. thermal sensor specifications at recommended operating conditions (see ?recommended operating conditions (1) ? on page 16 ) characteristic min max unit temperature range (1) 0 127 c comparator settling time (2)(3) 20 ? s resolution (3) 4? c accuracy (3) -12 +12 c adhesive or thermal interface material heat sink heat sink clip printed circuit board option bga package
20 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 6.1.4 adhesives and thermal interface materials figure 6-3. thermal performance of select thermal interface material a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications w here the heat sink is attached by spring clip mecha- nism, figure 6-3 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroe ther oil), a bare joint, and a joint with t hermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing con- tact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 6-2 on page 19 ). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. the board designer can choose between several types of thermal interface. heat sink adhesive materi- als should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. 0 0.5 1 1.5 2 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin2/w) 0 1020304050607080
21 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 6.1.5 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-ca se thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value specified in ?recommended operating conditions (1) ? on page 16 . the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10c. the thermal resistance of the thermal inter- face material ( int ) is typically about 1c/w. assuming a t a of 30c, a t r of 5 o c, a cbga package jc = 0.03, and a power consumption (p d ) of 5.0 watts, the following expression for t j is obtained: die-junction temperature: t j = 30c + 5c + (0.03c/w + 1.0c/w + sa ) 5.0 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity is shown in figure 6-4 . figure 6-4. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity 1 3 5 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pinfin heat sink approach air velocity (m/s) (25 x28 x 15 mm) 2 4 6 heat sink thermal resistance c/w)
22 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 assuming an air velocity of 0. 5 m/s, we have an effective r sa of 7c/w, thus t j = 30c + 5c+ (0.03c/w +1.0c/w + 7c/w) 5.0 w resulting in a die-junction temperature of approximately 81c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wakefield engineering, and aavid engi- neering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig- ure-of-merit used for comparing the thermal per formance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal manage- ment because no single parameter can adequately descr ibe three-dimensional heat flow. the final die- junction operating temperature, is not only a functi on of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component?s power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat flux of adjacent components), heat sink effici ency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s micro- electronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. for these reasons , we recommend using conjugate heat transfer models for the board, as well as, system-leve l designs. to expedite system-leve l thermal analysis, several ?com- pact? thermal-package models are available within flotherm ? . these are available upon request. 7. power consideration 7.1 power management the pc755 provides four power modes, selectable by setting the appropriate control bits in the msr and hido registers. the four power modes are as follows: full-power: this is the default power state of the pc755. the pc755 is fully powered and the internal functional units operate at the full processor clock speed. if the dynamic power management mode is enabled, functional unit s that are idle will automatically ente r a low-power state without affecting performance, software execution, or external hardware. doze: all the functional units of the pc755 are disabled except for the time base/decrementer registers and the bus snooping logic. when the proc essor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the pc755 into the full-power state. the pc755 in doze mode maintains the pll in a fully powered state and locked to the system external clock input (sysclk) so a transition to the full- power state takes only a few processor clock cycles. nap: the nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the pll in a powered state. the pc755 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (mcp). a return to full-power state from a nap state takes only a few processor clock cycles. when the processor is in nap mode, if qack is negated, the processor is put in doze mode to support snooping.
23 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 sleep: sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the ppl and susclk. returning the pc755 to the full-power state requires the enabling of the ppl and sysclk, followed by the asserti on of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check input (mcp) signal after the time required to relock the ppl. 7.2 power dissipation notes: 1. these values apply for all valid processor bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically < 10% of v dd power. worst case power consumption for av dd = 15 mw and l2av dd = 15 mw. 2. maximum power is measured at nominal v dd (see ?recommended operating conditions (1) ? on page 16 ) while running an entirely cache-resident, contrived sequence of instructions which keep the execu- tion units maximally busy. 3. typical power is an average value measured at the nominal recommended v dd (see ?recommended operating conditions (1) ? on page 16 ) and 65c in a system while running a typical code sequence. 4. not 100% tested. characterized and periodically sampled. table 7-1. power consumption for pc755 processor (cpu) frequency unit 300 mhz 350 mhz 400 mhz full-power mode typical (1)(3)(4) 3.1 3.6 5.4 w maximum (1)(2) 4.5 6 8 w doze mode maximum (1)(2)(4) 1.822.3w nap mode maximum (1)(2)(4) 111w sleep mode maximum (1)(2)(4) 550 550 550 mw sleep mode-pll and dll disabled maximum (1)(2) 510 510 510 mw
24 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 8. electrical characteristics 8.1 static characteristics notes: 1. nominal voltages; see ?recommended operating conditions (1) ? on page 16 . 2. for processor bus signals, the reference is ov dd while l2ov dd is the reference for the l2 bus signals. 3. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk) and ieee 1 149.1 boundary scan (jtag) signals. 4. capacitance is periodically sampled rather than 100% tested. 5. the leakage is measured for nominal ov dd and v dd , or both ov dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or - 5%). 8.2 dynamic characteristics after fabrication, parts are sorted by maxi mum processor core frequency as shown in ?clock ac specifi- cations? on page 25 and tested for conformance to the ac specifications for that frequency. these specifications are for 275, 300, 333 mhz processor core frequencies. the processor core frequency is determined by the bus (sysclk) frequency and the se ttings of the pll_cfg[0-3] signals. parts are sold by maximum proc essor core frequency. table 8-1. dc electrical specifications at recommended operating conditions (see ?recommended operating condi- tions (1) ? on page 16 ) characteristic nominal bus voltag e (1) symbol min max unit input high voltage (all inputs except syslck) (2)(3) 2.5 v ih 1.6 (l2)ov dd + 0.3 v 3.3 v ih 2 (l2)ov dd + 0.3 v input low voltage (all inputs except syslck) (2) 2.5 v il -0.3 0.6 v 3.3 v il -0.3 0.8 v sysclk input high voltage 2.5 kv ih 1.8 ov dd + 0.3 v 3.3 kv ih 2.4 ov dd + 0.3 v sysclk input low voltage 2.5 kv il -0.3 0.4 v 3.3 kv il -0.3 0.4 v input leakage current, (2)(3) v in = l2ov dd /ov dd i in ?10a hi-z (off-state) leakage current, (2)(3)(5) v in = l2ov dd /ov dd i tsi ?10a output high voltage, i oh = - 6 ma 2.5 v oh 1.7 ? v 3.3 v oh 2.4 ? v output low voltage, i ol = 6 ma 2.5 v ol ?0.45v 3.3 v ol ?0.4v capacitance, v in = 0v, f = 1 mhz (3)(4) c in ?5pf
25 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 8.2.1 clock ac specifications table 8-2 provides the clock ac timing specifications as defined in ?absolute maximum ratings (1) ? on page 14 . notes: 1. caution: the sysclk frequency and pll_cfg[0 - 3] settings must be chosen such that the resulting sysclk (bus) fre- quency, cpu (core) frequency, and pll (vco) frequency do no t exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0 - 3] signal description in table 9-1 on page 39 ,? for valid pll_cfg[0 - 3] settings. 2. rise and fall times measurements are now specified in terms of slew rates, rather th an time to account fo r selectable i/o bus interface levels. the minimum slew rate of 1v/ns is equivalent to a 2ns maximum rise/fall time measured at 0.4v and 2.4v or a rise/fall time of 1ns measured at 0.4v to 1.4v. 3. timing is guaranteed by design and characterization. 4. this represents total input jitter ? short term and long term combined and is guaranteed by design. 5. relock timing is guaranteed by design and characterization. pll - relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reac hed during the power - on reset sequence. this specification also applies when the pll has been disabled and subsequently re - enabled during sleep mode . also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll - relock time during the power - on reset sequence. figure 8-1 provides the sysclk input timing diagram. figure 8-1. sysclk input timing diagram 8.2.1.1 processor bus ac specifications table 8-3 on page 26 provides the processor bus ac timing specifications for the pc755 as defined in figure 8-2 on page 26 and figure 8-4 on page 28 . timing specifications for the l2 bus are provided in ?l2 clock ac specifications? on page 28 . table 8-2. clock ac timing specifications at re commended operating conditions (see ?recommended operating conditions (1) ? on page 16 ) characteristic symbol maximum processor core frequency unit 300 mhz 350 mhz 400 mhz min max min max min max processor frequency (1) f core 200 300 200 350 200 400 mhz vco frequency (1) f vco 400 600 400 700 400 800 mhz sysclk frequency (1) f sysclk 25 100 25 100 25 100 mhz sysclk cycle time t sysclk 10 40 10 40 10 40 ns sysclk rise and fall time (2) t kr & t kf ?2?2?2 ns t kr & t kf ?1.4?1.4?1.4 ns sysclk duty cycle measured at ov dd /2 (3) t khkl /t sysclk 40 60 40 60 40 60 % sysclk jitter (3)(4) ? 150 ? 150 ? 150 ps internal pll relock time (3)(5) ?100?100?100 s s ysclk vm vm vm kv ih kv il vm = midpoint voltage (ov dd /2 ) t sysclk t kr t kf t khkl
26 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 notes: 1. all input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are m easured from the midpoint of the rising edge of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 ? load (see figure 8-2 ). input and output timings are measured at the pin; time - of - flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbology used for timing specifications herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the hi gh (h) state or input setup time. and t khov symbolizes the time from sysclk(k) going highs) until outputs (o) are valid (v) or output valid time. input hold time can be read as the time that the input signa l (i) went invalid (x) with respect to the rising clock edge (kh) - note the position of the refe rence and its state for inputs ? and output hold time can be read as the time from the rising edg e (kh) until the output went invalid (ox). for additional explana- tion of ac timing specifications in freescale powerpc microprocessors, see the application note ?understanding ac timing specifications for powerpc microprocessors.? 3. the setup and hold time is with respect to the rising edge of hreset (see figure 8-2 ). 4. this specification is for configuration mode select onl y. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll re - lock time during the power - on reset sequence. 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time durati on (in nanoseconds) of t he parameter in question. 6. mode select signals are bvsel, l2vsel, pll_cfg[0 - 3] 7. guaranteed by design and characterization. 8. bus mode select pins must remain stab le during operation. changi ng the logic states of bvsel or l2vsel during operation will cause the bus mode voltage selection to change. changing the logic states of the pll_cfg pins during operation will cause the pll division ratio selection to change. both of th ese conditions are considered outs ide the specification and are not supported. once hreset is negated the states of the bus mode selection pins must remain stable. figure 8-2 provides the mode select input timing diagram for the pc755. figure 8-2. mode input timing diagram table 8-3. processor bus mode selectio n ac timing specifications (1) at v dd = a v dd = 2.0v 100 mv; -55 t j +125 c, ov dd = 3.3v 165 mv and ov dd = 1.8v 100 mv and ov dd = 2.0v 100 mv parameter symbols (2) all speed grades unit min max mode select input setup to hreset (3)(4)(5)(6)(7) t mvrh 8?t sysclk hreset to mode select input hold (3)(4)(6)(7)(8) t mxrh 0?ns hreset mode signals vm t mvrh t mxrh vm = midpoint voltage (ov dd /2)
27 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 figure 8-3 provides the ac test load for the pc755. figure 8-3. ac test load notes: 1. revisions prior to rev 2.8 (rev e) were limited in perfor mance and did not conform to this specification. contact your local freescale sales office for more information. 2. guaranteed by design and characterization. 3. t sysclk is the period of the external clock (sysclk) in nanoseco nds (ns). the numbers given in the table must be multiplied by the period of sysclk to comp ute the actual time du ration (in ns) of the parameter in question. 4. per the 60x bus protocol, ts , abb and dbb are driven only by the currently active bus master. they are asserted low then precharged high before returning to high-z as shown in figure 6-1 on page 18 . the nominal precharge width for ts , abb or dbb is 0.5 x t sysclk , i.e. less than the minimum t sysclk period, to ensure that another master asserting ts , abb , or dbb on the following clock will not contend with the precharge. output valid and output hold timing is tested for the signal asserted. out - put valid time is tested for precharge.t he high-z behavior is guaranteed by design. 5. per the 60x bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue since any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high-z for one cloc k before precharging it high during the second cycle after th e assertion of aack . the nominal precharge width for artry is 1.0 t sysclk ; i.e., it should be high-z as shown in figure 6-1 on page 18 before the first opportunity for another master to assert artry . output valid and output hold timing is tested for the signal asserted. output valid time is tested for precharge. the high-z and precharge behavior is guaranteed by design. ov dd /2 output z 0 = 50 ? r l = 50 ? table 8-4. processor bus ac timing specifications (1) at recommended operating conditions parameter symbols all speed grades unit min max setup times: all inputs t ivkh 2.5 ? ns input hold times: tlbisync , mcp , smi t ixkh 0.6 ? ns input hold times: all inputs, except tlbisync , mcp , smi t ixkh 0.2 ? ns valid times: all outputs t khov ?4.1ns output hold times: all outputs t khox 1?ns sysclk to output enable (2) t khoe 0.5 ? ns sysclk to output high impedance (all except abb , artry , dbb ) (2) t khoz ?6ns sysclk to abb , dbb high impedance after precharge (2)(3)(4) t khabpz ?1t sysclk maximum delay to artry precharge (2)(3)(5) t kharp ?1t sysclk sysclk to artry high impedance after precharge (2)(3)(5) t kharpz ?2t sysclk
28 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 figure 8-4 provides the input/output timing diagram for the pc755. figure 8-4. input/output timing diagram 8.2.1.2 l2 clock ac specifications the l2clk frequency is programmed by the l2 configuration register (l2cr[4:6]) core-to-l2 divisor ratio. see table 8-5 on page 29 for example core and l2 frequencies at various divisors. table 8-5 pro- vides the potential range of l2clk output ac timing specifications as defined in figure 8-5 on page 30 . the minimum l2clk frequency of table 8-5 is specified by the maximum de lay of the inte rnal dll. the variable-tap dll introduces up to a full clock period delay in the l2clkouta, l2clkoutb, and l2sync_out signals so that the returning l2sync_in signal is phase aligned with the next core clock (divided by the l2 divisor ratio). do not choose a core-to-l2 divisor which results in an l2 frequency below this minimum, or the l2clkout signals prov ided for sram clocking will not be phase aligned with the pc755 core clock at the srams. the maximum l2clk frequency shown in table 8-5 is the core frequency divided by one. very few l2 sram designs will be able to operate in this mode. most designs will se lect a greater core-to-l2 divisor to provide a longer l2clk period for read and write access to the l2 srams. the maximum l2clk fre- quency for any application of the pc755 will be a function of the ac timings of the pc75 5, the ac timings for the sram, bus loading, and printed circuit board trace length. freescale is similarly limited by system constraints and cannot perform tests of the l2 interface on a socketed part on a functional tester at the maximum frequencies of table 8-5 . therefore functional oper- ation and ac timing information are tested at core-to-l2 divisors of 2 or greater. functionality of core-to- l2 divisors of 1 or 1.5 is verified at less than maximum rated frequencies. sysclk all inputs vm vm all outputs (except ts, abb, artry, dbb) try ar vm t ivkh t ixkh t khoe t khov t khox t khabpz t khov t khox t khoz t kharpz t khov t khox t kharp t khov t khoz vm = midpoint voltage (ov dd /2 or v in /2) ts, abb, dbb
29 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 l2 input and outp ut signals are latched or en abled respectively by the in ternal l2clk (which is sysclk multiplied up to the core frequency and divided down to the l2clk frequency). in other words, the ac timings of table 8-6 on page 31 and table 8-7 on page 32 are entirely independent of l2sync_in. in a closed loop system, where l2sync_in is driv en through the board trace by l2sync_out, l2sync_in only controls the output phase of l2clkouta and l2clkoutb which are used to latch or enable data at the srams. however, since in a clos ed loop system l2sync_in is held in phase align- ment with the internal l2clk, the signals of table 8-6 and table 8-7 are referenced to this signal rather than the not-externally-visible internal l2clk. duri ng manufacturing test, these times are actually mea- sured relative to sysclk. the l2sync_out signal is intended to be routed halfway out to the srams and then returned to the l2sync_in input of the pc755 to synchronize l2clko ut at the sram with the processor?s internal clock. l2clkout at the sram can be offset forward or backward in time by shortening or lengthening the routing of l2sync_out to l2sync_in. see freescale application note an179/d ?powerpc ? backside l2 timing analysis for the pcb design engineer.? the l2clkouta and l2clkoutb signals should not have more than two loads. notes: 1. l2clk outputs are l2clk_outa, l2clk_outb, l2clk_ out and l2sync_out pins. the l2clk frequency to core fre- quency settings must be chosen so that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. the maximum l2lck frequency will be system dependent. l2clk_outa and l2clk_outb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measur ed at midpoint voltage. 3. the dll re - lock time is specified in terms of l2clks. the number in the table must be multiplied by the period of l2clk to compute the actual time duration in nanoseconds. re - lock timing is guaranteed by design and characterization. 4. the l2cr[l2sl] bit should be set for l2clk frequencies less th an 110 mhz. this adds more delay to each tap of the dll. 5. allowable skew between l2sync_out and l2sync_in. 6. this output jitter number repres ents the maximum delay of one tap forward or one tap back from the current dll tap as the phase comparator seeks to minimize the phase difference be tween l2sync_in and the internal l2clk. this number must be comprehended in the l2 timing analysis. the input jitter on sysclk affects l2clkout a nd the l2 addre ss/data/control signals equally and therefore is already comprehended in the ac timing and does not have to be considered in the l2 timing analysis. 7. guaranteed by design. table 8-5. l2clk output ac timing specification. at v dd = a v dd = 2.0v 100 mv; -55 t j +125 c, ov dd = 3.3v 165 mv and ov dd = 1.8v 100 mv and ov dd = 2.0v 100 mv parameter symbols all speed grades unit min max l2clk frequency (1)(4) f l2clk 80 450 mhz l2clk cycle time t l2clk 2.5 12.5 ns l2clk duty cycle (2)(7) t chcl /t l2clk 45 55 % internal dll - relock time (3)(7) ? 640 ? l2clk dll capture window (5)(7) ? 0 10 ns l2clkout output - to - output skew (6)(7) t l2cskw ?50ps l2clkout output jitter (6)(7) ? ? 150 ps
30 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 the l2clk_out timing diagram is shown in figure 8-5 . figure 8-5. l2clk_out output timing diagram vm = midpoint voltage (l2ovdd/2) l2clk_outa l2clk_outb l2 differential clock mode l2 single-ended clock mode l2sync_out l2clk_outa vm t l2cr t l2cf vm vm vm l2clk_outb vm vm vm vm vm l2sync_out vm vm vm vm vm vm vm vm t l2cskw t l2clk t l2clk t chcl t chcl
31 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 8.2.1.3 l2 bus input ac specifications table 8-6 provides the l2 bus interface ac timing specifications for the pc755 as defined in figure 8-6 on page 32 and figure 8-7 on page 32 for the loading conditions described in figure 8-8 on page 32 . notes: 1. rise and fall times for the l2sync_in input are measured from 20% to 80% of l2ov dd . 2. all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input l2sync_in (see figure 6-3 on page 20 ). input timings are measured at the pins. 3. all output specifications are me asured from the midpoint voltage of the rising edge of l2sync_in to the midpoint of the sig- nal in question. the output timings ar e measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 8-1 on page 25 ). 4. the outputs are valid for both single-ended and differential l2clk modes. for pipelined registered synchronous bur- strams, l2cr[14 - 15] = 01 or 10 is recommended. for pipelined late write synchronous burstrams, l2cr[14 - 15] = 11 is recommended. 5. guaranteed by design and characterization. 6. revisions prior to rev 2.8 (rev e) were limited in performance. and did not conform to this spec ification. contact your local e2v sales office for more information. table 8-6. l2 bus interface ac timing specifications at recommended operating conditions parameter symbol all speed grades unit min max l2sync_in rise and fall time (1) t l2cr & t l2cf ?1.0ns setup times: data and parity (2) t dvl2ch 1.2 - ns input hold times: data and parity (2) t dxl2ch 0-ns valid times: (3)(4) all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2chov - - - - 3.1 3.2 3.3 3.7 ns output hold times: (3) all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2chox 0.5 0.7 0.9 1.1 - - - - ns l2sync_in to high impedance: (3)(5) all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2choz - - - - 2.4 2.6 2.8 3.0 ns
32 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 figure 8-6 shows the l2 bus input timing diagrams for the pc755. figure 8-6. l2 bus input timing diagrams figure 8-7 shows the l2 bus output timing diagrams for the pc755. figure 8-7. l2 bus output timing diagrams figure 8-8 provides the ac test load for l2 interface of the pc755. figure 8-8. ac test load for the l2 interface 8.2.2 ieee 1149.1 ac timing specifications table 8-7 provides the ieee 1149.1 (jtag) ac timing specificatio ns as defined in figure 8-9 on page 33 , figure 8-10 on page 33 , figure 8-11 on page 34 , and figure 8-12 on page 34 . l2sync_in vm vm = midpoint voltage (l2ov dd /2) t dvl2ch t dxl2ch t l2cr t l2cf l2 data and data parity inputs l2sync_in vm vm = midpoint voltage (l2ov dd /2) vm l2data bus t l2chox t l2choz t l2chov all outputs output l2ovdd/2 r l = 50 ? z 0 = 50 ? table 8-7. jtag ac timing specificatio ns (independent of sysclk) (1) parameter symbol min max unit tck frequency of operation f tclk 016mhz tck cycle time f tclk 62.5 - ns tck clock pulse width measured at 1.4v t jhjl 31 - ns tck rise and fall times t jr & t jf 02ns trst assert time (2) ttrst 25 - ns
33 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 notes: 1. all outputs are measured from the midpoint voltage of th e falling/rising edge of tclk to the midpoint of the signal in ques- tion. the output timings are measured at the pins . all output timings assume a purely resistive 50 ? load (see figure 8-9 ). time - of - flight delays must be added for trace lengths, vias, and connectors in the system. 2. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 3. non - jtag signal input timing with respect to tck. 4. non - jtag signal output timing with respect to tck. 5. guaranteed by design and characterization. figure 8-9 provides the ac test load for tdo and the boundary-scan outputs of the pc755. figure 8-9. alternate ac test load for the jtag interface figure 8-10 provides the jtag clock input timing diagram. figure 8-10. jtag clock input timing diagram input setup times: (3) - boundary - scan data - tms, tdi t dvjh t ivjh 4 0 - - ns input hold times: (3) - boundary - scan data - tms, tdi t dxjh t ixjh 15 12 - - ns valid times: (4) - boundary - scan data - tdo t jldv t jlov - - 4 4 ns output hold times: (4) - boundary - scan data - tdo t jldv t jlov 25 12 - - ns tck to output high impedance: (4)(5) - boundary - scan data - tdo t jldz t jloz 3 3 19 9 ns table 8-7. jtag ac timing specificatio ns (independent of sysclk) (1) (continued) parameter symbol min max unit ov dd /2 output z 0 = 50 ? r l = 50 ? tclk vm vm vm vm = midpoint voltage (ov dd /2 ) t tclk t jr t jf t jhjl
34 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 figure 8-11 provides the trst timing diagram. figure 8-11. trst timing diagram figure 8-12 provides the boundary-scan timing diagram. figure 8-12. boundary-scan timing diagram figure 8-13 provides the test access port timing diagram. figure 8-13. test access port timing diagram trst t trst vm = midpoint voltage (ov dd /2) vm vm vm vm tck boundary data inputs boundary data outputs boundary data outputs vm = midpoint voltage (ov dd /2) t dxjh t dvjh t jldv t jldz output data valid t jldh output data valid input data valid tck tdi, tms tdo tdo vm vm t ixjh t ivjh t jlov t jloz t jloh vm = midpoint voltage (ov dd /2) output data valid input data valid output data valid
35 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 8.2.2.1 jtag configuration signals boundary scan testing is enabled throug h the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all pr ocessors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power- on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must bemerged into these signals with logic. the arrangement shown in figure 8-14 on page 36 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0 ? isolation resistor so that it is asserted when the sys temreset signal (hreset ) is asserted ensuring that the jtag scan chain is ini- tialized during power-on. while freescale recommends that the cop header be designed into the system as shown in figure 8-14 , if this is not possible, the isolati on resistor will allow future access to trst in the case where a jtag interfacemay need to be wired onto the system in debug situations. the cop header shown in figure 8-14 adds many benefits ? breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this inter- face ? and can be as inexpensive as an unpopulated footprint for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key.
36 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 figure 8-14. jtag interface connection notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented on the pc755. connect pin 5 of the cop header to ov dd with a 10 k ? pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drain type output and does not actively deassert qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag inte rface is not implemented, connect hreset from the target source to trst of the part through a 0 ? isolation resistor. the cop header shown in figure 8-15 on page 37 adds many benefits?breakpoints, watchpoints, reg- ister and memory examination/modification and other standard debugger features are possible through this interface ? and can be as inexpensive as an unpopulated footprint for a header to be added when needed. hreset from target board sources 13 sreset sreset nc nc 11 vdd_sense 6 5 1 15 2k ? 10 k ? 10 k ? 10 k ? chkstp_in 8 tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 key 10 k ? 10 k ? 10 k ? 10 k ? qack qack chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k ? 4 hreset sreset ov dd ov dd ov dd ov dd ov dd ov dd ov dd ov dd chkstp_in tms tdo tdi tck qack trst chkstp_out ov dd ov dd 1 2k ? 3 0 ? 5 hreset 10 k ?
37 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 the cop interface has a standard header for connection to the target system, based on the 0.025? square-post 0.100? centered header assembly (often called a ?berg? header). the connector typically has pin 14 removed as a connector key. figure 8-15 shows the cop connector diagram. figure 8-15. cop connector diagram there is no standardized way to number the cop header shown in figure 8-15 ; consequently, many dif- ferent pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin one (as with an ic). regardless of the numbering, the signal placement recom- mended in figure 8-15 is common to all known emulators. the qack signal shown in table 8-7 on page 32 is usually hooked up to the pci bridge chip in a system and is an input to the pc755 informing it that it can go into the quiescent state. under normal operation this occurs during a low power mode selection. in order for cop to work the pc755 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. to preserve correct power down operation, qack should be merged so that it also can be driven by the pci bridge. 3 ck stp_out 13 9 5 1 6 10 2 top view 15 11 7 16 12 8 4 key no pi n hreset sreset tm s run/st op tck tdi tdo ground trst vdd_sense pins 10, 12 and 14 are no-connects. pin 14 is not physically pres ent qack chkstp_ in
38 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 9. preparation for delivery 9.1 packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. 9.2 certificate of compliance e2v offers a certificate of compliances with each shipment of parts, affirming the products are in compli- ance either with mil-prf-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. 9.3 handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the following handling practices are recommended: 1. devices should be handled on benches with conductive and grounded surfaces 2. ground test equipment, tools and operator 3. do not handle devices by the leads 4. store devices in conductive foam or carriers 5. avoid use of plastic, rubber, or silk in mos areas 6. maintain relative humidity above 50 percent if practical 7. for ci-cga packages, use specific tray to take care of the highest height of the package com- pared with the normal cbga
39 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 9.4 clock relationship choices the pc755?s pll is co nfigured by the pl l_cfg[0-3] signals. for a give n sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the pc755 is shown in figure 10-2 on page 41 for example frequencies. notes: 1. pll_cfg[0:3] settings not listed are reserved. 2. the sample bus-to-core frequencies show n are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not suppor ted, or not tested for by the pc755; see ?clock ac specifications? on page 25 for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is in tended for factory use and emulator tool use only. note: the ac timing specifications given in th is document do not apply in pll-bypass mode. 4. in pll off mode, no clocking occurs inside the pc755 regardless of the sysclk input. table 9-1. pc755 microprocessor pll configuration pll_cfg [0-3] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to vco multiplier bus 33 mhz bus 50 mhz bus 66 mhz bus 75 mhz bus 80 mhz bus 100 mhz 0100 2x 2x ----- 200 (400) 1000 3x 2x - - 200 (400) 225 (450) 240 (480) 300 (600) 1110 3.5x 2x - - 233 (466) 263 (525) 280 (560) 350 (700) 1010 4x 2x - 200 (400) 266 (533) 300 (600) 320 (640) 400 (800) 0111 4.5x 2x - 225 (450) 300 (600) 338 (675) 360 (720) - 1011 5x 2x - 250 (500) 333 (666) 375 (750) 400 (800) - 1001 5.5x 2x - 275 (550) 366 5733 --- 1101 6x 2x 200 (400) 300 (600) 400 (800) --- 0101 6.5x 2x 216 (433) 325 (650) ---- 0010 7x 2x 233 (466) 350 (700) ---- 0001 7.5x 2x 250 (500) 375 (750) ---- 1100 8x 2x 266 (533) 400 (800) ---- 0110 10x 2x 333 (666) ----- 0011 pll off/bypass pll off, sysclk clocks core circuitry directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs
40 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 the pc755 generates the clock for the external l2 sy nchronous data srams by dividing the core clock frequency of the pc755. the divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (dll) circuit and should be routed from the pc755 to the external rams. a separate clock output, l2sync_out is sent out half the distance to the srams and then returned as an input to the dll on pin l2sync_in so that the rising-edge of the clock as seen at the external rams can be aligned to the clocking of the internal latches in the l2 bus interface. the core-to-l2 frequency divisor for the l2 pll is selected through the l2clk bits of the l2cr register. generally, the divisor must be chosen according to the frequency supported by the external rams, the frequency of the pc755 core, and the phase adjustment range that the l2 dll supports. figure 8-9 on page 33 shows various example l2 clock frequencies that can be obtained for a given set of core fre- quencies. the minimum l2 frequency target is 80 mhz. note: the core and l2 frequencies are for reference only. some examples may represent core or l2 frequencies which are not useful, not supported, or not tested for by the pc755; see ?l2 clock ac specifications? on page 28 for valid l2clk frequencies. the l2cr[l2sl] bi t should be set for l2clk frequencies less than 110 mhz. table 9-2. sample core-to-l2 frequencies core frequency in mhz 1 1.5 2 2.5 3 250 250 166 125 100 83 266 266 177 133 106 89 275 275 183 138 110 92 300 300 200 150 120 100 325 325 217 163 130 108 333 333 222 167 133 111 350 350 233 175 140 117 366 366 244 183 146 122 375 375 250 188 150 125 400 400 266 200 160 133
41 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 10. system design information 10.1 pll power supply filtering the av dd and l2av dd power signals are provided on the pc755 to provide power to the clock genera- tion phase-locked loop and l2 cache delay-locked loop resp ectively. to ensure st ability of the internal clock, the power supplied to the av dd input signal should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 10-2 using surface mount capacitors with minimum effective series indu ctance (esl) is recommended. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. the circuit should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. an identical but separ ate circuit should be placed as close as possible to the l2av dd pin. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 360 bga footprint, without the inductance of vias. the l2av dd pin may be more difficult to route but is pro- portionately less critical. figure 10-1. pll power supply filter circuit 10.2 power supply voltage sequencing the notes in figure 10-3 on page 43 contain cautions about the sequencing of the external bus voltages and core voltage of the pc755 (when they are different). these cautions are necessary for the long term reliability of the part. if they are violated, the esd (e lectrostatic discharge) prot ection diodes will be for- ward biased and excessive current can flow thr ough these diodes. if the system power supply design does not control the voltage sequencing, the circuit of figure 10-3 can be added to meet these require- ments. the mur420 schottky diodes of figure 10-3 control the maximum potential difference between the external bus and core power supplies on powe r-up and the 1n5820 diodes regulate the maximum potential difference on power-down. figure 10-2. example voltage sequencing circuit v dd av dd (or l2av dd ) 10 ? 2.2 f 2.2 f gnd low esl surface mount capacitors 3.3v 2.0v murs320 1n5820 murs320 1n5820
42 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 10.3 decoupling recommendations due to the pc755?s dynamic power management feature, large address and data buses, and high oper- ating frequencies, the pc755 can generate transient power surges and high frequency noise in its power supply, especially while driv ing large capacitive loads. this noise must be prevented from reaching other components in the pc755 system, and the pc755 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the syste m designer place at least one decoupling capacitor at each v dd , o v dd , and l2ov dd pin of the pc755. it is also recommended that these decoupling capacitors receive their power from separate v dd , (l2)ov dd and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 f or 0.1 f. only ceramic smt (surface mount technol- ogy) capacitors should be used to minimize lead indu ctance, preferably 0508 or 0603 orientations where connections are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , l2o v dd , and ov vplanes, to enable quick rechar ging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be c onnected to the power and ground planes through two vias to minimize inductance. suggested bulk ca pacitors ? 100-330 f (avx tps tantalum or sanyo oscon). 10.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level through a resistor. unused active low inputs should be tied to o v dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , o v dd , l2o v dd , and gnd pins of the pc755. 10.5 output buffer dc impedance the pc755 60x and l2 i/o drivers are characterized over process, voltage, and temperature. to mea- sure z 0 , an external resistor is connected from the chip pad to (l2)ov dd or gnd. then, the value of each resistor is varied until the pad voltage is (l2)o v dd /2 (see figure 10-4 on page 43 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals (l2)o v dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals (l2)o v dd /2. r p then becomes the resistance of the pull-up devices. no tag describes the driver impedance measurement circuit described above.
43 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 figure 10-3. driver impedance measurement circuit alternately, the following is another method to determine the output impedance of the pc755. a voltage source, v force , is connected to the output of the pc755 as in figure 10-4 . data is held low, the voltage source is set to a value that is equal to (l2)o v dd /2 and the current sourced by v force is measured. the voltage drop across the pull-down device, which is equal to (l2)o v dd /2, is divided by the measured cur- rent to determine the output impedance of the pull-down device, r n . similarly, the impedance of the pull- up device is determined by dividing the voltage drop of the pull-up, (l2)o v dd /2, by the current sank by the pull-up when the data is high and v force is equal to (l2)o v dd /2. this method can be employed with either empirical data from a test set up or with data from simulation models, such as ibis. r p and r n are designed to be close to each other in value. then z 0 = (r p + r n )/2. figure 10-4 describes the alternate driver impedance measurement circuit. figure 10-4. alternate driver impedance measurement circuit (l2)ov dd ognd r p r n pad data sw1 sw2 (l2)ov dd (l2)ov dd bga da ta pi n ognd vforce
44 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 table 10-1 summarizes the signal impedance results. the driver impedance values were characterized at 0c, 65c, and 105c. the impedance increases with junction temperature and is relatively unaf- fected by bus voltage. 10.6 pull - up resistor requirements the pc755 requires pull-up resistors (1 k ? ? 5 k ? ) on several control pins of the bus interface to main- tain the control signals in the negated state after they have been actively negated and released by the processor or other bus masters. these pins are ts , abb , aack , artry , dbb , dbwo , ta , tea , and dbdis . drtry should also be connected to a pull-up resistor (1 k ? ? 5 k ? ) if it will be used by the sys- tem; otherwise, this signal should be connected to hreset to select no-drtry mode. three test pins also require pull-up resistors (100 ? ? 1 k ? ). these pins are l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ov dd for normal machine operation. in addition, ckstp_out is an open-drain style output that requires a pull-up resistor (1 k ? ? 5 k ? ) if it is used by the system. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. since the pro- cessor must continually monitor these signals fo r snooping, this float c ondition may cause additional power draw by the input receivers on the processor or by other rece ivers in the system. these signals can be pulled up through weak (10 k ? ) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this addi tional power draw, but address bus pull-up resistors are not necessary for proper device operation. the snooped address and transfer attribute inputs are: a[0:31], ap[0:3], tt[0:4], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and, there- fore, do not require pull-up resistors on the bus. other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. the data bus signals are: dh[0:31], dl[0:31], and dp[0:7]. if 32-bit data bus mo de is selected, the input rece ivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they wo uld otherwise normally be driven. for this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. if address or data parity is not used by the system , and the respective parity checking is disabled through hid0, the input receivers for those pins are disabled , and those pins do not require pull-up resistors and should be left unconnect ed by the system. if all parity generation is disabled through hid0, then all parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. table 10-1. impedance characteristics. v dd = 2.0v, ov dd = 3.3v, t c = 0 - 105c impedance processor bus l2 bus symbol unit rn 25-36 25-36 z 0 w rp 26-39 26-39 z 0 w
45 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 11. package mechanical data the following sections provide the package parameter s and mechanical dimensions for the pc745, 255 pbga package as well as the pc755, 360 cbga and pbga packages. while both the pc755 plastic and the ceramic packages are described here, both packages are not guaranteed to be available at the same time. all new designs should a llow for either ceramic or plastic bga packages for this device. for more information on designing a common footprint for both plastic and ceramic package types, please contact your local e2v sales office. 11.1 package parameters for the pc745 the package parameters are as provided in the follo wing list. the package type is 21 21 mm, 255-lead plastic ball grid array (pbga). table 11-1. package parameters parameter hitce pbga package outline 21 21 mm 21 21 mm interconnects 255 (16 16 ball array ? 1) 255 (16 16 ball array ? 1) pitch 1.27 mm (50 mil) 1.27 mm (50 mil) minimum module height 2.42 2.25 mm maximum module height 3.08 2.80 mm ball diameter (typical) 0.89 mm (35 mil) 0.75 mm (29.5 mil)
46 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 11.1.1 mechanical dimensions of the pc745 hitce package figure 11-1 provides the mechanical dimensions and bottom surface nomenclature of the pc745, 255 hitce package. figure 11-1. mechanical dimensions and bottom surface nomenclature of the pc745 hitce b c 255x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b dim min max a 2.42 3.08 a1 0.8 1.0 a2 0.90 1.14 b 0.82 0.93 d d1 e e1 e 1.27 bsc 21.00 bsc 21.00 bsc 7.87 6.75 millimeters 0.2 d 2x a1 corner e 0.2 b a c 0.2 c e1 d1 a a1 a2 1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array 4. capacitor pads may be unpopulated
47 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 11.1.2 mechanical dimensions of the pc745 pbga package figure 11-2 provides the mechanical dimensions and bottom surface nomenclature of the pc745, 255 pbga package. figure 11-2. mechanical dimensions and bottom surface nomenclature of the pc745 pbga 11.2 package parameter for the pc755 the package parameters are as provided in the following list. the package type is 25 x 25 mm, 360-lead plastic ball grid array (pbga). b c 255x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b dim min max a 2.25 2.80 a1 0.50 0.70 a2 1.00 1.20 b 0.60 0.90 d d1 e e1 e 1.27 bsc 21.00 bsc 21.00 bsc 7.87 6.75 millimeters 0.2 d 2x a1 corner e 0.2 b a c 0.2 c e1 d1 a a1 a2 1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array 4. capacitor pads may be unpopulated table 11-2. package parameters parameter hitce-cbga pbga package outline 25 mm 25 mm 25 mm 25 mm interconnects 360 (19 x 19 ball array ? 1) 360 (19 x 19 ball array ? 1 pitch 1.27 mm (50 mil) 1.27 mm (50 mil) minimum module height 2,65 mm 2.22 mm maximum module height 3,2 mm 2.77 mm ball diameter 0,89 mm (35 mil) 0.75 mm (29.5 mil)
48 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 11.2.1 mechanical dimensions of the pc755 pbga figure 11-3 provides the mechanical dimensions and bottom surface nomenclature of the pc755, 360 pbga package. figure 11-3. mechanical dimensions and bottom surface nomenclature of the pc755 pbga notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array 0.2 360x d 2x a1 corner e e 0.2 2x b a 12345678910111213141516 a b c d e f g h j k l m n p r t b c 0.2 c 171819 u w v millimeters dim min max a 2.22 2.77 a1 0.50 0.70 a2 1.00 1.20 a3 ?0.60 b 0.60 0.90 d 25.00 bsc d1 6.75 e 25.00 bsc e1 7.87 e 1.27 bsc e1 d1 a a1 a2 a3 1 b c a 0.3 c 0.15
49 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 11.2.2 mechanical dimensions of the pc755 cbga package figure 11-4 provides the mechanical dimensions and bottom surface nomenclature of the pc755, 360 cbga package. figure 11-4. mechanical dimensions and bottom surface nomenclature of pc755 (cbga) b c 360x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b a a1 a2 c c 171819 u w v millimeters dim min max a 2.65 3.20 a1 0.8 1 a2 1.10 1.30 a3 ?0.60 b 0.82 0.93 d 25.00 bsc d1 6.75 e 25.00 bsc e1 7.87 e 1.27 bsc 0.2 d 2x a1 corner e 0.2 2x a e1 d1 a3 1 0.15 b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array
50 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 11.2.3 mechanical dimensions of the pc755 hitce package figure 11-5 provides the mechanical dimensions and bottom surface nomenclature of the pc755, 360 hitce package. figure 11-5. mechanical dimensions and bottom surface nomenclature of pc755 (hitce) b c 360x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b a1 a2 c 0.15 c 171819 u w v millimeters dim min max a 2.65 3.24 a1 0.8 1 a2 1.10 1.30 a3 ?0.60 b 0.82 0.93 d 25.00 bsc d1 6.75 e 25.00 bsc e1 7.87 e 1.27 bsc 0.2 d 2x a1 corner e 0.2 2x a e1 d1 a3 1 b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array a
51 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 11.2.4 mechanical dimensions of the pc755 ci-cga package figure 11-6 provides the mechanical dimensions and bottom surface nomenclature of pc755, 360 ci- cga package. figure 11-6. mechanical dimensions and bottom surface nomenclature of pc755 (ci-cga) b c 360x e 12345678910111213141516 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b a a4 a2 171819 u w v millimeters dim min max a 4.08 bsc a1 a2 1.10 1.30 1.545 1.695 a3 ?0.60 b 0.79 0.990 d 25.00 bsc d1 6.75 e 25.00 bsc e1 7.87 e 0.2 d 2x a1 corner e 0.2 2x a e1 d1 a3 a1 a6 a5 a4 0.82 0.9 a5 0.14 bsc a6 0.25 0.35 1.27 bsc b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array c b 0.15
52 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 12. ordering information figure 12-1. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. xx y xx nnn e part identifier 745/755 product code (1) pc(x) (2) package (1) max internal processor speed (1) revision level (1) temperature range t c /t j (1) x screening level u: upscreening test blank: standard e: rev. 2.8 zf: fc-pbga g: cbga gs: ci-cga gh: hitce bus divider (to be confirmed) 745 755 l 300 350 366 400 m: -55 c/+125 c v: -40 c/+110 c x process descriptor b: 300/350/366 mhz c: 400 mhz l: any valid pll configuration (mhz)
53 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 13. definitions 13.1 life support applications these products are not designed for use in life supp ort appliances, devices, or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnity e2v for any damages resulting from such improper use or sale. 14. document revision history table 14-1 provides a revision history for this hardware specification. table 14-1. revision history revision number date substantive change(s) 0828i 01/2008 change a1 specification from 0.79/0.99 mm to 0.8/1 mm in figure 11-4 on page 49 and figure 11-5 on page 50 . change t j to t c on page 1 and 16 . 0828h 02/2007 name change from atmel to e2v 2138g 04/2006 increased power specification for 350 mhz full-power mode in table 7-1 on page 23 updated ordering information to new template 2138f 05/2005 added hitce package for powerpc 745 removed phrase " for the ceramic ball grid array (cbga) package " from section 6.1.3 on page 19 ; this information applies to devices in all packages figure 8-14 on page 36 : updated cop connector diagram to recommend a weak pull-up resistor on tck 2138e 10/2004 product specification release subs equent to product qualification motorola changed to freescale 2138d 06/2003 preliminary -site
i 0828i?hirel?01/08 e2v semiconductors sas 2008 pc755/745 table of contents features ................. .............. .............. .............. .............. .............. ............. 1 description ......... ................. .............. .............. .............. .............. ............. 1 screening ........... ................. .............. .............. .............. .............. ............. 1 1 general description .. ................. ................ ................. ................ ............. 2 1.1 simplified block diagram ........................................................................................ 2 1.2 general parameters ................................................................................................3 1.3 features .................................................................................................................. 3 2 pin assignments .......... ................ ................ ................. .............. ............. 6 2.1 pinout listings ......................................................................................................... 8 3 signal description .............. .............. .............. .............. .............. ........... 13 4 detailed specifications ........ .............. .............. .............. .............. ......... 14 5 applicable documents ........... ................. ................ ................. ............. 14 5.1 design and construction ....................................................................................... 14 6 thermal characteristics ......... ................. ................ ................. ............. 17 6.1 package characteristics ........................................................................................ 17 7 power consideration ............ .............. .............. .............. .............. ......... 22 7.1 power management ..............................................................................................22 7.2 power dissipation .................................................................................................. 23 8 electrical characteristics ... .............. .............. .............. .............. ........... 24 8.1 static characteristics ............................................................................................. 24 8.2 dynamic characteristics ........................................................................................ 24 9 preparation for delivery ....... .............. .............. .............. .............. ......... 38 9.1 packaging .............................................................................................................. 38 9.2 certificate of compliance ...................................................................................... 38 9.3 handling ................................................................................................................ 38 9.4 clock relationship choices ................................................................................... 39 10 system design information ... ................. ................ ................. ............. 41 10.1 pll power supply filtering ................................................................................. 41 10.2 power supply voltage sequencing ..................................................................... 41 10.3 decoupling recommendations ........................................................................... 42
ii 0828i?hirel?01/08 pc755/745 e2v semiconductors sas 2008 10.4 connection recommendations ........................................................................... 42 10.5 output buffer dc impedance .............................................................................. 42 10.6 pull-up resistor requirements ............................................................................ 44 11 package mechanical data ...... ................. ................ ................. ............. 45 11.1 package parameters for the pc745 .................................................................... 45 11.2 package parameter for the pc755 ..................................................................... 47 12 ordering information ............ .............. .............. .............. .............. ......... 52 13 definitions ............. .............. .............. .............. .............. .............. ........... 53 13.1 life support applications ..................................................................................... 53 14 document revision history .. ............. .............. .............. .............. ......... 53 table of contents ......... ................ ................ ................. ................ ............ i
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